1. Field of the Invention
The present invention relates to an electronic part packaging structure and, more particularly, an electronic part embedded in an insulating layer and mounted.
2. Description of the Related Art
In the prior art, there is an electronic part packaging structure having a structure in which the electronic part such as the semiconductor chip, the stacked capacitor chip, or the like is embedded in the insulating layer. As shown in FIG. 1, in a semiconductor chip 100 in the prior art, a predetermined element (not shown) such as a transistor, or the like and connection pads 112 connected thereto are provided on the element forming surface side of a semiconductor substrate 110. Also, a passivating film 104 in which opening portions 104x are provided on the connection pads 112 is formed on the semiconductor chip 100, and also a contact portion 112a made of an Ni/Au layer is formed on the connection pads 112 in the opening portions 104x, respectively.
Then, as shown in FIG. 2, bumps 108 made of solder, or the like are provided in the contact portions 112a of the semiconductor chip 100 having such a structure. Then, a circuit board 200 having through electrodes 202 and wiring patterns 204 connected to the through electrodes 202 is prepared, and then the bumps 108 of the semiconductor chip 100 are flip-chip connected to the wiring patterns 204. Then, an underfill resin 210 is filled in a clearance between the semiconductor chip 100 and the circuit board 200, and then an interlayer insulating film 212 for covering the semiconductor chip 100 is formed.
Then, via holes 212x are formed in the interlayer insulating film 212 on the wiring patterns 204, and then upper wiring patterns 204a connected to the wiring pattern 204 via the via hole 212x are formed. In this manner, the semiconductor chip 100 is mounted such that the connection pads 112 are connected electrically to the wiring patterns 204 on the circuit board 200 in a state such that the semiconductor chip 100 is embedded in the interlayer insulating layer 212.
In this event, in some cases the semiconductor chip 100 is mounted onto the circuit board 200 to direct the connection pads 112 upward and then the contact portions 112a and the wiring patterns 204 of the circuit board 200 are connected via wires.
Also, as shown in FIG. 3, in a stacked capacitor chip 300 in the prior art, a plurality of first electrode layers 302 and a plurality of second electrode layers 304 are stacked via a dielectric layer 306 to constitute a capacitor portion. The first electrode layers 302 are connected to a first connection terminal 310, and the second electrode layers 304 are connected to a second connection terminal 312. Then, a protection layer 308 is provided on an uppermost surface and a lowermost surface of the capacitor portion of the stacked capacitor chip 300 respectively.
Then, as shown in FIG. 4, in the stacked capacitor chip 300 having such a structure, a bump 118 is provided on bottom surfaces of the first connection terminal 310 and the second connection terminal 312, respectively. Then, the bumps 118 of the stacked capacitor chip 300 are connected electrically to the wiring patterns 204 of the same circuit board 200 as in FIG. 2. Then, the interlayer insulating film 212 for covering the stacked capacitor chip 300 is formed and, like FIG. 2, the upper wiring patterns 204a connected to the wiring pattern 204, respectively, via the via hole 212x provided in the interlayer insulating film 212 are formed on the interlayer insulating film 212. In this manner, the stacked capacitor chip 300 is mounted such that the first and second connection terminals 310, 312 are connected electrically to the wiring patterns 204 on the circuit board 200 in a state such that the stacked capacitor chip 300 is embedded in the interlayer insulating layer 212.
Also, as the technology connected with the electronic part packaging structure in above FIG. 2, in Patent Literature 1 (Patent Application Publication (KOKAI) 2000-323645), there is set forth a semiconductor device having a structure such that a plurality of semiconductor chips are mounted three- dimensionally on the circuit board in a state that these chips are embedded in the insulating layer and also these semiconductor chips are connected mutually by wiring patterns that are formed in a multi-layered fashion via insulating layers.
As described above, in the electronic part packaging method in the prior art, such a premise is assumed that the semiconductor chip 100 is connected electrically to the wiring patterns 204 on the circuit board 200 via the flip-chip connection or the wire bonding. Therefore, the connection pads 112 (contact portions 112a) must be exposed by providing the opening portions 104x in the passivating film 104 of the semiconductor chip 100. For this reason, a problem lies such that the passivating film 104 is limited to material that is easily patterned and is relatively expensive such as photosensitive resin, printable insulating material, or the like.
In addition, in the semiconductor chip 100 in the prior art, the contact portion (Ni/Au layer) 112a must be particularly provided on the connection pads 112 to prevent corrosion of the connection pads 112 and to insure the reliability of the electrical connection between the connection pads 112 and the bumps 108. As a result, such provision of the contact portions acts as one factor that results in an increase of cost.
Further, in the stacked capacitor chip 300 in the prior art, the first and second connection terminals 310, 312 made of copper, or the like are not covered with the passivating film and are held in an exposed condition. Therefore, the situation in which corrosion resistance is poor and the reliability becomes an issue may be supposed.